Attending:

Notes by :

• Focal Plane layout + Noise (Karl)
• Initiating simulations (Julian)
• Readout mux factor, wire count (Roger?)
• Temperature stability from Planck?

Hi Shaul,

We're at about 3.2W per module assuming FPGA technology and existing DAC/ADCs that are flight qualified. Changing to ASICs could bring this down slightly, but not a lot (the FPGA is about 25% of the power, if I remember correctly).

The power does not go up much if the mux factor per module increases - so getting to 128x or 256x is very helpful in power consumption. The warm readout can support this already. The cold readout is limited by strays to increase the mux factor, and its hard to predict where we'll end up there. If I were choosing a target, I would specify a goal of 200x, and baseline of 128x (375W for 15,000 detectors). Real investment in the cold system would be needed to get there. Kam Arnold at UCSD and Toki Suzuki at Berkeley are the main ones working on this. Moving the SQUIDs to the cryogenic stage can help.

       Matt