********** Mapped Logic ********** |
$OpTx$FX_DC$4 <= ((NOT MHOCON)
OR (NOT NOVALIM2 AND NOVALIM1) OR (NOT KRLIM2 AND KRLIM1)); |
CO2_1CON <= (NOT PFI4.PIN AND NOT PFI5.PIN); |
CO2_2CON <= (PFI4.PIN AND NOT PFI5.PIN); |
CO2_3CON <= (NOT PFI4.PIN AND PFI5.PIN); |
CO2_4CON <= (PFI4.PIN AND PFI5.PIN); |
DUMPCON <= PFI9; |
LINCON <= PFI8; |
MIXCON <= PFI7; |
PFI2 <= NOT ((($OpTx$FX_DC$4.LFBK)
OR (MIXLIM1 AND NOT MIXLIM2 AND NOT CO2LIM2 AND CO2LIM1) OR (MIXLIM1 AND NOT MIXLIM2 AND NOT ARLIM2 AND ARLIM1))); |
PFI3 <= NOT ((($OpTx$FX_DC$4.LFBK)
OR (NOT CO2LIM2 AND CO2LIM1) OR (NOT ARLIM2 AND ARLIM1))); |
FTCPE_PFI4: FTCPE port map (PFI4,'1',NOT PFI5_OBUF/PFI5_OBUF_CLKF.LFBK,'0','0'); |
FTCPE_PFI5: FTCPE port map (PFI5,PFI4_OBUF.LFBK,NOT PFI5_OBUF/PFI5_OBUF_CLKF.LFBK,'0','0'); |
PFI5_OBUF/PFI5_OBUF_CLKF <= (NOT PFI6 AND NOT CPLDCON1); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |