cpldfit:  version P.49d                             Xilinx Inc.
                                  Fitter Report
Design Name: mixer_controller                    Date:  7-27-2015,  3:52PM
Device Used: XC9572-15-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
13 /72  ( 18%) 20  /360  (  6%) 21 /144 ( 15%)   2  /72  (  3%) 27 /69  ( 39%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           7/18        5/36        5           7/90       7/18
FB2           6/18       16/36       16          13/90       4/17
FB3           0/18        0/36        0           0/90       0/17
FB4           0/18        0/36        0           0/90       0/17
             -----       -----                   -----       -----     
             13/72       21/144                  20/360     11/69 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   16          16    |  I/O              :    27      63
Output        :    9           9    |  GCK/IO           :     0       3
Bidirectional :    2           2    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 13 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'mixer_controller.ise'.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal                    Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                      Pts   Inps          No.  Type    Use     Mode Rate State
LINCON                    1     1     FB1_1   4    I/O     O       STD  FAST 
CO2_3CON                  1     2     FB1_3   6    I/O     O       STD  FAST 
CO2_2CON                  1     2     FB1_4   7    I/O     O       STD  FAST 
DUMPCON                   1     1     FB1_5   2    I/O     O       STD  FAST 
MIXCON                    1     1     FB1_6   3    I/O     O       STD  FAST 
CO2_1CON                  1     2     FB1_7   11   I/O     O       STD  FAST 
CO2_4CON                  1     2     FB1_8   5    I/O     O       STD  FAST 
PFI2                      3     7     FB2_10  75   I/O     O       STD  FAST 
PFI3                      3     5     FB2_12  79   I/O     O       STD  FAST 
PFI4                      1     1     FB2_13  80   I/O     I/O     STD  FAST RESET
PFI5                      2     2     FB2_14  81   I/O     I/O     STD  FAST RESET

** 2 Buried Nodes **

Signal                    Total Total Loc     Pwr  Reg Init
Name                      Pts   Inps          Mode State
PFI5_OBUF/PFI5_OBUF_CLKF  1     2     FB2_17  STD  
$OpTx$FX_DC$4             3     5     FB2_18  STD  

** 16 Inputs **

Signal                    Loc     Pin  Pin     Pin     
Name                              No.  Type    Use     
PFI9                      FB1_2   1    I/O     I
CO2LIM1                   FB1_10  13   I/O     I
ARLIM2                    FB1_12  18   I/O     I
ARLIM1                    FB1_13  20   I/O     I
CO2LIM2                   FB1_15  14   I/O     I
NOVALIM2                  FB1_17  15   I/O     I
KRLIM2                    FB1_18  24   I/O     I
PFI7                      FB2_15  83   I/O     I
PFI6                      FB2_16  82   I/O     I
PFI8                      FB2_17  84   I/O     I
NOVALIM1                  FB3_2   17   I/O     I
MIXLIM2                   FB3_5   19   I/O     I
MHOCON                    FB3_7   35   I/O     I
MIXLIM1                   FB3_8   21   I/O     I
KRLIM1                    FB3_9   26   I/O     I
CPLDCON1                  FB4_15  65   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               5/31
Number of signals used by logic mapping into function block:  5
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
LINCON                1       0     0   4     FB1_1   4     I/O     O
(unused)              0       0     0   5     FB1_2   1     I/O     I
CO2_3CON              1       0     0   4     FB1_3   6     I/O     O
CO2_2CON              1       0     0   4     FB1_4   7     I/O     O
DUMPCON               1       0     0   4     FB1_5   2     I/O     O
MIXCON                1       0     0   4     FB1_6   3     I/O     O
CO2_1CON              1       0     0   4     FB1_7   11    I/O     O
CO2_4CON              1       0     0   4     FB1_8   5     I/O     O
(unused)              0       0     0   5     FB1_9   9     GCK/I/O 
(unused)              0       0     0   5     FB1_10  13    I/O     I
(unused)              0       0     0   5     FB1_11  10    GCK/I/O 
(unused)              0       0     0   5     FB1_12  18    I/O     I
(unused)              0       0     0   5     FB1_13  20    I/O     I
(unused)              0       0     0   5     FB1_14  12    GCK/I/O 
(unused)              0       0     0   5     FB1_15  14    I/O     I
(unused)              0       0     0   5     FB1_16  23    I/O     
(unused)              0       0     0   5     FB1_17  15    I/O     I
(unused)              0       0     0   5     FB1_18  24    I/O     I

Signals Used by Logic in Function Block
  1: PFI4.PIN           3: PFI7               5: PFI9 
  2: PFI5.PIN           4: PFI8             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LINCON               ...X.................................... 1       1
CO2_3CON             XX...................................... 2       2
CO2_2CON             XX...................................... 2       2
DUMPCON              ....X................................... 1       1
MIXCON               ..X..................................... 1       1
CO2_1CON             XX...................................... 2       2
CO2_4CON             XX...................................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               16/20
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   63    I/O     
(unused)              0       0     0   5     FB2_2   69    I/O     
(unused)              0       0     0   5     FB2_3   67    I/O     
(unused)              0       0     0   5     FB2_4   68    I/O     
(unused)              0       0     0   5     FB2_5   70    I/O     
(unused)              0       0     0   5     FB2_6   71    I/O     
(unused)              0       0     0   5     FB2_7   76    GTS/I/O 
(unused)              0       0     0   5     FB2_8   72    I/O     
(unused)              0       0     0   5     FB2_9   74    GSR/I/O 
PFI2                  3       0     0   2     FB2_10  75    I/O     O
(unused)              0       0     0   5     FB2_11  77    GTS/I/O 
PFI3                  3       0     0   2     FB2_12  79    I/O     O
PFI4                  1       0     0   4     FB2_13  80    I/O     I/O
PFI5                  2       0     0   3     FB2_14  81    I/O     I/O
(unused)              0       0     0   5     FB2_15  83    I/O     I
(unused)              0       0     0   5     FB2_16  82    I/O     I
PFI5_OBUF/PFI5_OBUF_CLKF
                      1       0     0   4     FB2_17  84    I/O     I
$OpTx$FX_DC$4         3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$4.LFBK   7: KRLIM1            12: NOVALIM1 
  2: ARLIM1               8: KRLIM2            13: NOVALIM2 
  3: ARLIM2               9: MHOCON            14: PFI4_OBUF.LFBK 
  4: CO2LIM1             10: MIXLIM1           15: PFI5_OBUF/PFI5_OBUF_CLKF.LFBK 
  5: CO2LIM2             11: MIXLIM2           16: PFI6 
  6: CPLDCON1           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
PFI2                 XXXXX....XX............................. 7       7
PFI3                 XXXXX................................... 5       5
PFI4                 ..............X......................... 1       1
PFI5                 .............XX......................... 2       2
PFI5_OBUF/PFI5_OBUF_CLKF 
                     .....X.........X........................ 2       2
$OpTx$FX_DC$4        ......XXX..XX........................... 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1   25    I/O     
(unused)              0       0     0   5     FB3_2   17    I/O     I
(unused)              0       0     0   5     FB3_3   31    I/O     
(unused)              0       0     0   5     FB3_4   32    I/O     
(unused)              0       0     0   5     FB3_5   19    I/O     I
(unused)              0       0     0   5     FB3_6   34    I/O     
(unused)              0       0     0   5     FB3_7   35    I/O     I
(unused)              0       0     0   5     FB3_8   21    I/O     I
(unused)              0       0     0   5     FB3_9   26    I/O     I
(unused)              0       0     0   5     FB3_10  40    I/O     
(unused)              0       0     0   5     FB3_11  33    I/O     
(unused)              0       0     0   5     FB3_12  41    I/O     
(unused)              0       0     0   5     FB3_13  43    I/O     
(unused)              0       0     0   5     FB3_14  36    I/O     
(unused)              0       0     0   5     FB3_15  37    I/O     
(unused)              0       0     0   5     FB3_16  45    I/O     
(unused)              0       0     0   5     FB3_17  39    I/O     
(unused)              0       0     0   5     FB3_18        (b)     
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1   46    I/O     
(unused)              0       0     0   5     FB4_2   44    I/O     
(unused)              0       0     0   5     FB4_3   51    I/O     
(unused)              0       0     0   5     FB4_4   52    I/O     
(unused)              0       0     0   5     FB4_5   47    I/O     
(unused)              0       0     0   5     FB4_6   54    I/O     
(unused)              0       0     0   5     FB4_7   55    I/O     
(unused)              0       0     0   5     FB4_8   48    I/O     
(unused)              0       0     0   5     FB4_9   50    I/O     
(unused)              0       0     0   5     FB4_10  57    I/O     
(unused)              0       0     0   5     FB4_11  53    I/O     
(unused)              0       0     0   5     FB4_12  58    I/O     
(unused)              0       0     0   5     FB4_13  61    I/O     
(unused)              0       0     0   5     FB4_14  56    I/O     
(unused)              0       0     0   5     FB4_15  65    I/O     I
(unused)              0       0     0   5     FB4_16  62    I/O     
(unused)              0       0     0   5     FB4_17  66    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$4 <= ((NOT MHOCON)
	OR (NOT NOVALIM2 AND NOVALIM1)
	OR (NOT KRLIM2 AND KRLIM1));


CO2_1CON <= (NOT PFI4.PIN AND NOT PFI5.PIN);


CO2_2CON <= (PFI4.PIN AND NOT PFI5.PIN);


CO2_3CON <= (NOT PFI4.PIN AND PFI5.PIN);


CO2_4CON <= (PFI4.PIN AND PFI5.PIN);


DUMPCON <= PFI9;


LINCON <= PFI8;


MIXCON <= PFI7;


PFI2 <= NOT ((($OpTx$FX_DC$4.LFBK)
	OR (MIXLIM1 AND NOT MIXLIM2 AND NOT CO2LIM2 AND CO2LIM1)
	OR (MIXLIM1 AND NOT MIXLIM2 AND NOT ARLIM2 AND ARLIM1)));


PFI3 <= NOT ((($OpTx$FX_DC$4.LFBK)
	OR (NOT CO2LIM2 AND CO2LIM1)
	OR (NOT ARLIM2 AND ARLIM1)));

FTCPE_PFI4: FTCPE port map (PFI4,'1',NOT PFI5_OBUF/PFI5_OBUF_CLKF.LFBK,'0','0');

FTCPE_PFI5: FTCPE port map (PFI5,PFI4_OBUF.LFBK,NOT PFI5_OBUF/PFI5_OBUF_CLKF.LFBK,'0','0');


PFI5_OBUF/PFI5_OBUF_CLKF <= (NOT PFI6 AND NOT CPLDCON1);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-15-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC9572-15-PC84                     65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 PFI9                             43 TIE                           
  2 DUMPCON                          44 TIE                           
  3 MIXCON                           45 TIE                           
  4 LINCON                           46 TIE                           
  5 CO2_4CON                         47 TIE                           
  6 CO2_3CON                         48 TIE                           
  7 CO2_2CON                         49 GND                           
  8 GND                              50 TIE                           
  9 TIE                              51 TIE                           
 10 TIE                              52 TIE                           
 11 CO2_1CON                         53 TIE                           
 12 TIE                              54 TIE                           
 13 CO2LIM1                          55 TIE                           
 14 CO2LIM2                          56 TIE                           
 15 NOVALIM2                         57 TIE                           
 16 GND                              58 TIE                           
 17 NOVALIM1                         59 TDO                           
 18 ARLIM2                           60 GND                           
 19 MIXLIM2                          61 TIE                           
 20 ARLIM1                           62 TIE                           
 21 MIXLIM1                          63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 CPLDCON1                      
 24 KRLIM2                           66 TIE                           
 25 TIE                              67 TIE                           
 26 KRLIM1                           68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 PFI2                          
 34 TIE                              76 TIE                           
 35 MHOCON                           77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 PFI3                          
 38 VCC                              80 PFI4                          
 39 TIE                              81 PFI5                          
 40 TIE                              82 PFI6                          
 41 TIE                              83 PFI7                          
 42 GND                              84 PFI8                          


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-15-PC84
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25