Design Name | mixer_controller |
Device, Speed (SpeedFile Version) | XC9572, -15 (3.0) |
Date Created | Mon Jul 27 15:52:27 2015 |
Created By | Timing Report Generator: version P.49d |
Copyright | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Possible asynchronous logic: Clock pin 'PFI4.CLKF' has multiple original clock nets 'CPLDCON1' 'PFI6'. |
Possible asynchronous logic: Clock pin 'PFI5.CLKF' has multiple original clock nets 'CPLDCON1' 'PFI6'. |
Performance Summary | |
---|---|
Min. Clock Period | 14.000 ns. |
Max. Clock Frequency (fSYSTEM) | 71.429 MHz. |
Limited by Clock Pulse Width for CPLDCON1 | |
Clock to Setup (tCYC) | 10.500 ns. |
Pad to Pad Delay (tPD) | 24.500 ns. |
Clock Pad to Output Pad Delay (tCO) | 36.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 10.5 | 1 | 1 |
AUTO_TS_P2P | 0.0 | 36.5 | 35 | 35 |
AUTO_TS_P2F | 0.0 | 16.5 | 4 | 4 |
AUTO_TS_F2P | 0.0 | 20.0 | 10 | 10 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
PFI4.Q to PFI5.D | 0.000 | 10.500 | -10.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CPLDCON1 to CO2_1CON | 0.000 | 36.500 | -36.500 |
CPLDCON1 to CO2_2CON | 0.000 | 36.500 | -36.500 |
CPLDCON1 to CO2_3CON | 0.000 | 36.500 | -36.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CPLDCON1 to PFI4.CLKF | 0.000 | 16.500 | -16.500 |
CPLDCON1 to PFI5.CLKF | 0.000 | 16.500 | -16.500 |
PFI6 to PFI4.CLKF | 0.000 | 16.500 | -16.500 |
PFI6 to PFI5.CLKF | 0.000 | 16.500 | -16.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
PFI4.Q to CO2_1CON | 0.000 | 20.000 | -20.000 |
PFI4.Q to CO2_2CON | 0.000 | 20.000 | -20.000 |
PFI4.Q to CO2_3CON | 0.000 | 20.000 | -20.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
CPLDCON1 | 71.429 | Limited by Clock Pulse Width for CPLDCON1 |
PFI6 | 71.429 | Limited by Clock Pulse Width for PFI6 |
Destination Pad | Clock (edge) to Pad |
---|---|
CO2_1CON | 36.500 |
CO2_2CON | 36.500 |
CO2_3CON | 36.500 |
CO2_4CON | 36.500 |
PFI4 | 21.500 |
PFI5 | 21.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
CO2_1CON | 36.500 |
CO2_2CON | 36.500 |
CO2_3CON | 36.500 |
CO2_4CON | 36.500 |
PFI4 | 21.500 |
PFI5 | 21.500 |
Source | Destination | Delay |
---|---|---|
PFI4.Q | PFI5.D | 10.500 |
Source | Destination | Delay |
---|---|---|
PFI4.Q | PFI5.D | 10.500 |
Source Pad | Destination Pad | Delay |
---|---|---|
KRLIM1 | PFI2 | 24.500 |
KRLIM1 | PFI3 | 24.500 |
KRLIM2 | PFI2 | 24.500 |
KRLIM2 | PFI3 | 24.500 |
MHOCON | PFI2 | 24.500 |
MHOCON | PFI3 | 24.500 |
NOVALIM1 | PFI2 | 24.500 |
NOVALIM1 | PFI3 | 24.500 |
NOVALIM2 | PFI2 | 24.500 |
NOVALIM2 | PFI3 | 24.500 |
ARLIM1 | PFI2 | 15.000 |
ARLIM1 | PFI3 | 15.000 |
ARLIM2 | PFI2 | 15.000 |
ARLIM2 | PFI3 | 15.000 |
CO2LIM1 | PFI2 | 15.000 |
CO2LIM1 | PFI3 | 15.000 |
CO2LIM2 | PFI2 | 15.000 |
CO2LIM2 | PFI3 | 15.000 |
MIXLIM1 | PFI2 | 15.000 |
MIXLIM2 | PFI2 | 15.000 |
PFI7 | MIXCON | 15.000 |
PFI8 | LINCON | 15.000 |
PFI9 | DUMPCON | 15.000 |